Peripheral Interfacing - Practice MCQs for CCAT

Correct Answer: D - PPI (Programmable Peripheral Interface)

8255 is PPI - provides 3 ports for parallel I/O.

Correct Answer: D - 3

8255 has 3 ports: Port A, Port B, Port C.

Correct Answer: B - Programmable Interval Timer

8254 is a programmable timer/counter.

Correct Answer: B - Programmable Interrupt Controller

8259 PIC manages hardware interrupts.

Correct Answer: C - DMA Controller

8257 is a DMA controller for direct memory access.

Correct Answer: C - USART

8251 USART handles serial communication.

Correct Answer: B - 9 (1 master + 8 slaves)

8259 can cascade: 1 master + 8 slaves = 64 interrupt levels.

Correct Answer: C - Simple I/O (no handshaking)

Mode 0: Basic I/O without handshaking.

Correct Answer: C - 3

8254 has 3 independent 16-bit counters.

Correct Answer: D - Transfers data without CPU

DMA transfers data directly between I/O and memory without CPU.

Correct Answer: C - 3

The 8255 PPI has three 8-bit ports: Port A, Port B, and Port C. Port C can be further split into two 4-bit ports (upper and lower).

Correct Answer: C - 3

The 8255 supports three operating modes: Mode 0 (Simple I/O), Mode 1 (Strobed I/O with handshaking), and Mode 2 (Bi-directional bus for Port A only).

Correct Answer: B - Simple I/O or Basic Input/Output mode

Mode 0 is the simple (basic) I/O mode where ports are configured as simple input or output ports without handshaking. No interrupt capability is available in this mode.

Correct Answer: B - 11

The control word register is selected when A1=1 and A0=1 (address offset 11 binary or 03H). Port A=00, Port B=01, Port C=10, Control=11.

Correct Answer: A - I/O mode (mode definition)

When D7=1 in the control word, it indicates the I/O mode definition format, used to configure ports as input/output and select operating modes. D7=0 indicates BSR mode.

Correct Answer: D - Mode 2

Mode 2 is the bidirectional bus mode available only for Port A. It allows data to flow in both directions on Port A with handshaking signals from Port C.

Correct Answer: D - 3

The 8253 has three independent 16-bit counters (Counter 0, Counter 1, and Counter 2). Each counter can be programmed individually in different modes.

Correct Answer: D - 6

The 8253 supports 6 modes: Mode 0 (Interrupt on Terminal Count), Mode 1 (Hardware Retriggerable One-Shot), Mode 2 (Rate Generator), Mode 3 (Square Wave Generator), Mode 4 (Software Triggered Strobe), Mode 5 (Hardware Triggered Strobe).

Correct Answer: B - A low-going pulse for one clock period at the end of count

Mode 2 (Rate Generator) produces a low-going pulse for one clock period when the count reaches zero, then reloads and repeats. It acts as a divide-by-N counter.

Correct Answer: A - Mode 3

Mode 3 (Square Wave Generator) generates a continuous square wave. For even counts, the duty cycle is 50%. For odd counts N, output is high for (N+1)/2 and low for (N-1)/2 clocks.

Correct Answer: A - 8

A single 8259 PIC can handle 8 interrupt levels (IR0 to IR7). Multiple 8259s can be cascaded to handle up to 64 interrupt levels.

Correct Answer: B - 9 (up to 64 interrupts)

Up to 9 PICs can be cascaded: 1 master and 8 slaves, supporting up to 64 interrupt levels. Each slave connects to one of the 8 IR lines of the master.

Correct Answer: B - 4

The 8259 has 4 ICWs: ICW1 (initialization), ICW2 (vector address), ICW3 (cascade configuration), and ICW4 (additional parameters). ICW1 and ICW2 are mandatory; ICW3 and ICW4 are conditional.

Correct Answer: C - Masks or unmasks individual interrupt lines

OCW1 (Operation Command Word 1) is used to set the Interrupt Mask Register (IMR). Each bit corresponds to an IR line; setting a bit to 1 masks (disables) that interrupt.

Correct Answer: D - Interrupts that are currently being serviced

The ISR tracks which interrupt(s) are currently being processed by the CPU. A bit is set when an interrupt is acknowledged and cleared when an EOI command is issued.

Correct Answer: C - Clears the corresponding bit in the ISR

The EOI command clears the highest-priority bit in the ISR (In-Service Register), indicating that the interrupt service routine has completed, allowing lower-priority interrupts.

Correct Answer: B - 4

The 8257 has 4 independent DMA channels (CH0 to CH3). Each channel can handle data transfer between memory and an I/O device independently.

Correct Answer: B - 16384 bytes

Each DMA channel of the 8257 has a 14-bit terminal count register, allowing transfers of up to 2¹⁴ = 16,384 bytes in a single block transfer.

Correct Answer: D - HOLD/HRQ

The DMA controller sends a HOLD (or HRQ) signal to the CPU. The CPU completes the current machine cycle, tri-states its buses, and responds with HLDA (Hold Acknowledge).

Correct Answer: A - Cycle stealing mode

In cycle stealing (single transfer) mode, the DMA controller transfers one byte at a time and returns bus control to the CPU between each byte. This allows CPU and DMA to share the bus.

Correct Answer: D - Set or reset any bit of Port C

BSR mode (D7=0 in control word) allows individual bits of Port C to be set or reset without affecting other bits. Only Port C supports this feature.

Correct Answer: C - BCD or binary counting

Bits D1-D0 select BCD (D0=1) or binary (D0=0) counting. Bits D7-D6 select the counter, D5-D4 select read/write mode, and D3-D1 select the operating mode.

Correct Answer: B - Enables or disables counting

The GATE input enables or disables counting depending on the mode. In most modes, GATE must be HIGH for counting to proceed. In some modes, a rising edge on GATE triggers counting.

Correct Answer: B - Both fixed and rotating priority

The 8259 supports both fixed (fully nested) priority mode where IR0 has highest priority, and rotating priority mode where the last serviced interrupt gets lowest priority.

Correct Answer: A - Port C can be split into two 4-bit ports and provides handshaking signals

Port C can be split into upper 4 bits (PC4-PC7) and lower 4 bits (PC0-PC3), which can be independently configured. In Modes 1 and 2, Port C bits serve as handshaking and control signals.

Correct Answer: B - Fixed priority and rotating priority

The 8257 supports both fixed priority (CH0 highest to CH3 lowest) and rotating priority (last serviced channel gets lowest priority), configured through the mode register.

Correct Answer: C - 2 kHz

In Mode 2 (Rate Generator), Output frequency = Clock frequency / Count = 2 MHz / 1000 = 2 kHz. The counter divides the input clock by the loaded count value.

Correct Answer: A - Direct data transfer between memory and I/O without CPU intervention

DMA (Direct Memory Access) transfers data directly between memory and I/O devices without CPU involvement. The DMA controller takes over the bus and manages the transfer.

Correct Answer: D - Pending interrupt requests from IR lines

The IRR stores the status of interrupt request lines. When an IR pin goes active, the corresponding bit in the IRR is set, indicating a pending interrupt request.

Correct Answer: A - Counting Element (CE)

The Counting Element (CE) holds the current count being decremented. The Count Register (CR) holds the initial value loaded by the CPU, which is transferred to CE when counting begins.

Correct Answer: A - Handshaking and control signals

In Mode 1 (Strobed I/O), Port C bits are used for handshaking signals like STB (Strobe), IBF (Input Buffer Full), OBF (Output Buffer Full), ACK (Acknowledge), and INTR (Interrupt).

Correct Answer: A - CPU acknowledges and grants bus to DMA controller

HLDA (Hold Acknowledge) is sent by the CPU in response to HOLD/HRQ signal. It indicates that the CPU has tri-stated its buses and the DMA controller can take over the bus.

Correct Answer: D - Enabling interrupts of lower priority while servicing a higher priority interrupt

Special Mask Mode allows interrupts of any priority to be selectively enabled while a higher-priority interrupt is being serviced, overriding the normal priority mechanism.

Correct Answer: A - Both binary (16-bit) and BCD (4-decade)

The 8253/8254 can count in binary (0 to FFFF, 16-bit) or BCD (0 to 9999, 4-decade). The counting format is selected by bit D0 of the control word.

Correct Answer: C - 65536

In binary mode, loading a count of 0 results in the maximum count of 65536 (2¹⁶). The counter counts from the loaded value down to 0.

Correct Answer: A - Mode 1 and Mode 2

Mode 1 (Strobed I/O) and Mode 2 (Bidirectional) support handshaking with interrupt capability using Port C bits for control signals like STB, ACK, IBF, OBF, and INTR.

Correct Answer: D - By asserting the TC (Terminal Count) signal

The 8257 asserts the TC (Terminal Count) signal when the byte count reaches zero, indicating that the programmed number of bytes has been transferred.

Correct Answer: A - The upper 5 bits of the interrupt vector address

ICW2 specifies the upper 5 bits (A7-A3) of the interrupt vector address. The lower 3 bits are determined by the interrupt level (IR0-IR7). This maps interrupts to vector addresses.

Correct Answer: C - The control word is written

In Mode 0, the output initially goes LOW when the control word is written (or the mode is set). It goes HIGH when the terminal count (zero) is reached.

Correct Answer: A - Identify which slave PIC is requesting an interrupt during cascade mode

The 3 CAS lines (CAS0-CAS2) are used in cascade mode to identify which slave 8259 is requesting service. The master places the slave ID on these lines during the interrupt acknowledge cycle.