Interrupts — Practice MCQs for CCAT

Correct Answer: B — Generated by external device

Hardware interrupts come from external devices (keyboard, timer).

Correct Answer: B — Generated by instruction (INT n)

Software interrupts are executed by INT instruction.

Correct Answer: B — Disabled by software

Maskable interrupts can be enabled/disabled by software.

Correct Answer: B — Cannot be disabled

NMI cannot be disabled - highest priority hardware interrupt.

Correct Answer: B — Addresses of ISRs

IVT contains addresses of Interrupt Service Routines.

Correct Answer: B — Starting at address 0

8086 IVT is at memory locations 00000H to 003FFH.

Correct Answer: B — 4 bytes

Each vector is 4 bytes (2 bytes offset + 2 bytes segment).

Correct Answer: B — 256

8086 supports 256 interrupt types (0-255).

Correct Answer: B — Returns from ISR

IRET returns from interrupt service routine.

Correct Answer: B — Clears interrupt flag (disables interrupts)

CLI clears IF, disabling maskable interrupts.

Correct Answer: B — Interrupt triggered by executing an instruction

Software interrupt is generated by executing specific instructions (like INT in x86) rather than external hardware.

Correct Answer: B — CPU saves state and jumps to ISR

When interrupt occurs, CPU saves current state (flags, PC), then jumps to the Interrupt Service Routine.

Correct Answer: B — Order in which multiple simultaneous interrupts are handled

Interrupt priority determines which interrupt is serviced first when multiple interrupts occur simultaneously.

Correct Answer: B — Enables or disables maskable interrupts

Interrupt Flag controls whether maskable interrupts are enabled (IF=1) or disabled (IF=0).

Correct Answer: B — Software interrupts that jump to fixed locations

RST (Restart) are 1-byte software interrupt instructions that jump to specific memory locations (RST 0-7).

Correct Answer: B — Time from interrupt request to ISR execution start

Interrupt latency is the delay between interrupt assertion and when ISR begins executing.

Correct Answer: B — Higher priority interrupt interrupting current ISR

Nested interrupt occurs when a higher priority interrupt interrupts an ISR that is already executing.

Correct Answer: B — Manages multiple interrupt requests and prioritizes them

PIC accepts interrupt requests from multiple devices, prioritizes them, and sends one interrupt to CPU.

Correct Answer: B — CPU checking devices sequentially to find interrupt source

Polling is when CPU sequentially checks each device to identify which one caused the interrupt.

Correct Answer: B — Interrupt where device provides address of its ISR

In vectored interrupt, the interrupting device provides the address or vector number of its ISR.

Correct Answer: B — Enable Interrupts

EI (Enable Interrupt) sets the interrupt enable flip-flop, allowing maskable interrupts to be recognized.

Correct Answer: B — Disable Interrupts

DI (Disable Interrupt) clears the interrupt enable flip-flop, preventing maskable interrupts.

Correct Answer: B — CPU responding to interrupt request by reading vector

Interrupt acknowledge cycle is when CPU responds to interrupt request by signaling acknowledgment and reading interrupt vector.

Correct Answer: B — Edge detects signal transition, level detects signal state

Edge-triggered activates on signal transition (rising/falling edge). Level-triggered activates while signal is at specific level.

Correct Answer: B — Set Interrupt Flag (enable interrupts)

STI (Set Interrupt Flag) enables maskable interrupts by setting the IF flag to 1.