Interrupts - Practice MCQs for CCAT

Correct Answer: B - Generated by external device

Hardware interrupts come from external devices (keyboard, timer).

Correct Answer: C - Generated by instruction (INT n)

Software interrupts are executed by INT instruction.

Correct Answer: B - Disabled by software

Maskable interrupts can be enabled/disabled by software.

Correct Answer: D - Cannot be disabled

NMI cannot be disabled - highest priority hardware interrupt.

Correct Answer: B - Addresses of ISRs

IVT contains addresses of Interrupt Service Routines.

Correct Answer: D - Starting at address 0

8086 IVT is at memory locations 00000H to 003FFH.

Correct Answer: D - 4 bytes

Each vector is 4 bytes (2 bytes offset + 2 bytes segment).

Correct Answer: B - 256

8086 supports 256 interrupt types (0-255).

Correct Answer: A - Returns from ISR

IRET returns from interrupt service routine.

Correct Answer: A - Clears interrupt flag (disables interrupts)

CLI clears IF, disabling maskable interrupts.

Correct Answer: A - Interrupt triggered by executing an instruction

Software interrupt is generated by executing specific instructions (like INT in x86) rather than external hardware.

Correct Answer: B - CPU saves state and jumps to ISR

When interrupt occurs, CPU saves current state (flags, PC), then jumps to the Interrupt Service Routine.

Correct Answer: D - Order in which multiple simultaneous interrupts are handled

Interrupt priority determines which interrupt is serviced first when multiple interrupts occur simultaneously.

Correct Answer: B - Enables or disables maskable interrupts

Interrupt Flag controls whether maskable interrupts are enabled (IF=1) or disabled (IF=0).

Correct Answer: B - Software interrupts that jump to fixed locations

RST (Restart) are 1-byte software interrupt instructions that jump to specific memory locations (RST 0-7).

Correct Answer: D - Time from interrupt request to ISR execution start

Interrupt latency is the delay between interrupt assertion and when ISR begins executing.

Correct Answer: C - Higher priority interrupt interrupting current ISR

Nested interrupt occurs when a higher priority interrupt interrupts an ISR that is already executing.

Correct Answer: A - Manages multiple interrupt requests and prioritizes them

PIC accepts interrupt requests from multiple devices, prioritizes them, and sends one interrupt to CPU.

Correct Answer: A - CPU checking devices sequentially to find interrupt source

Polling is when CPU sequentially checks each device to identify which one caused the interrupt.

Correct Answer: B - Interrupt where device provides address of its ISR

In vectored interrupt, the interrupting device provides the address or vector number of its ISR.

Correct Answer: C - Enable Interrupts

EI (Enable Interrupt) sets the interrupt enable flip-flop, allowing maskable interrupts to be recognized.

Correct Answer: A - Disable Interrupts

DI (Disable Interrupt) clears the interrupt enable flip-flop, preventing maskable interrupts.

Correct Answer: C - CPU responding to interrupt request by reading vector

Interrupt acknowledge cycle is when CPU responds to interrupt request by signaling acknowledgment and reading interrupt vector.

Correct Answer: D - Edge detects signal transition, level detects signal state

Edge-triggered activates on signal transition (rising/falling edge). Level-triggered activates while signal is at specific level.

Correct Answer: D - Set Interrupt Flag (enable interrupts)

STI (Set Interrupt Flag) enables maskable interrupts by setting the IF flag to 1.

Correct Answer: C - 5

The 8085 has 5 hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. TRAP is non-maskable while the other four are maskable.

Correct Answer: A - TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR

The priority order from highest to lowest is: TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR. TRAP has the highest priority as it is non-maskable.

Correct Answer: A - EI

EI (Enable Interrupt) sets the interrupt enable flip-flop, allowing the 8085 to accept maskable interrupts (RST 7.5, RST 6.5, RST 5.5, and INTR).

Correct Answer: C - 0034H

RST 6.5 has a vector address of 0034H. The vector address is calculated as: interrupt number × 8 = 6.5 × 8 = 52 = 34H.

Correct Answer: C - 0024H

TRAP is vectored to address 0024H. It is the highest priority interrupt and is both edge and level triggered. Its vector address is fixed at 0024H.

Correct Answer: C - SIM

SIM (Set Interrupt Mask) is used to set the mask for RST 7.5, RST 6.5, and RST 5.5 interrupts. It also controls the SOD (Serial Output Data) line.

Correct Answer: A - Edge triggered only

RST 7.5 is edge triggered (positive edge). It has an internal flip-flop that is set on the rising edge of the interrupt signal and must be reset using SIM instruction.

Correct Answer: D - It expects the interrupting device to provide an instruction via data bus

INTR is a non-vectored interrupt. When accepted, the 8085 sends INTA signal and expects the external device to place an instruction (usually RST n) on the data bus.

Correct Answer: A - Read interrupt masks and pending interrupts

RIM (Read Interrupt Mask) reads the status of interrupt masks (M7.5, M6.5, M5.5), pending interrupts, interrupt enable status, and SID (Serial Input Data) into the accumulator.

Correct Answer: C - The interrupt system (interrupt enable flip-flop)

When an interrupt is acknowledged, the interrupt enable flip-flop is automatically reset, disabling further interrupts. EI must be executed in the ISR to re-enable interrupts.

Correct Answer: B - 256

The 8086 supports 256 interrupt types (INT 0 to INT 255). Each interrupt type has a 4-byte vector stored in the Interrupt Vector Table at memory addresses 00000H to 003FFH.

Correct Answer: B - At address 00000H to 003FFH

The IVT in 8086 occupies the first 1 KB of memory (00000H to 003FFH). It contains 256 entries, each 4 bytes (2 bytes for IP, 2 bytes for CS).

Correct Answer: A - INT 0

INT 0 (Divide Error) is automatically triggered when a DIV or IDIV instruction results in division by zero or when the quotient exceeds the destination register size.

Correct Answer: D - INT 2

INT 2 is the Non-Maskable Interrupt (NMI) in the 8086. It is triggered via the NMI pin and cannot be disabled by software. It is typically used for critical events.

Correct Answer: D - 002CH

RST 5.5 has a vector address of 002CH. The vector address = 5.5 × 8 = 44 = 2CH.

Correct Answer: B - Trap Flag (TF)

The Trap Flag (TF) enables single-step mode. When TF=1, the processor generates an INT 1 (single-step interrupt) after each instruction for debugging purposes.

Correct Answer: C - Disables all maskable interrupts

DI (Disable Interrupt) resets the interrupt enable flip-flop, preventing the processor from accepting maskable interrupts. TRAP cannot be disabled by DI.

Correct Answer: B - Enable masking of interrupts using bits D0-D2

MSE (Mask Set Enable, bit D3) must be 1 for the mask bits (D0=M5.5, D1=M6.5, D2=M7.5) to take effect. If MSE=0, the mask bits are ignored.

Correct Answer: A - D4 (R7.5)

Bit D4 (R7.5) in the SIM instruction is used to reset the RST 7.5 edge-triggered flip-flop. Setting this bit clears any pending RST 7.5 interrupt.

Correct Answer: C - Maskable hardware interrupts via INTR pin

The Interrupt Flag (IF) enables or disables maskable hardware interrupts arriving on the INTR pin. STI sets IF=1 (enable), CLI sets IF=0 (disable). NMI and software interrupts are unaffected.

Correct Answer: C - 4 bytes

Each entry in the 8086 IVT is 4 bytes: 2 bytes for the offset (IP) stored at the lower address, and 2 bytes for the segment (CS) stored at the higher address.

Correct Answer: D - Level triggered

RST 6.5 and RST 5.5 are level triggered interrupts. The interrupt signal must remain active (high) until acknowledged. Unlike RST 7.5 which is edge triggered.

Correct Answer: A - Only the program counter

When an interrupt is accepted, only the Program Counter (PC) is automatically saved on the stack. Registers and flags must be saved manually by the programmer in the ISR using PUSH instructions.

Correct Answer: D - Return from an interrupt service routine

IRET (Interrupt Return) pops IP, CS, and the flags register from the stack to return from an interrupt service routine. It restores the processor state to continue normal execution.

Correct Answer: B - RST 5

RST 0 through RST 7 are software interrupts (1-byte CALL instructions) in the 8085. RST 5 causes a jump to address 0028H (5 × 8 = 40 = 28H). TRAP, RST 7.5, and INTR are hardware interrupts.