8085 & 8086 Architecture - Practice MCQs for CCAT

Correct Answer: A - 8 bits

8085 is an 8-bit microprocessor with an 8-bit data bus for transferring data.

Correct Answer: A - 16 bits

8085 has a 16-bit address bus, allowing it to address up to 64KB (2¹⁶) of memory.

Correct Answer: C - 6

8085 has 6 general-purpose 8-bit registers: B, C, D, E, H, and L, which can be paired as BC, DE, HL.

Correct Answer: B - Address Latch Enable - separates address from multiplexed bus

ALE (Address Latch Enable) signals when valid address is on the lower 8 bits of the multiplexed address/data bus.

Correct Answer: B - 5

8085 has 5 flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY).

Correct Answer: C - 16 bits

8086 is a 16-bit microprocessor with a 16-bit data bus for transferring data.

Correct Answer: B - 20 bits

8086 has a 20-bit address bus, allowing it to address up to 1MB (2²⁰) of memory.

Correct Answer: B - BIU and EU

8086 has Bus Interface Unit (BIU) for fetching instructions and Execution Unit (EU) for executing them.

Correct Answer: C - Fetches instructions and handles bus operations

Bus Interface Unit (BIU) fetches instructions from memory, reads operands, and writes results to memory/ports.

Correct Answer: D - Decodes and executes instructions

Execution Unit (EU) decodes and executes instructions received from BIU using ALU and registers.

Correct Answer: A - 4

8086 has 4 segment registers: CS (Code), DS (Data), SS (Stack), and ES (Extra).

Correct Answer: B - Segment × 16 + Offset

Physical Address = Segment × 16 (shift left 4 bits) + Offset. This gives 20-bit address.

Correct Answer: D - 6 bytes

8086 has a 6-byte instruction prefetch queue in BIU for pipelining instruction fetch and execute.

Correct Answer: A - TRAP

TRAP is the highest priority interrupt in 8085 and is non-maskable.

Correct Answer: D - 003CH

RST 7.5 has vector address 003CH (7.5 × 8 = 60 = 3CH in hex).

Correct Answer: C - 5

8085 has 5 hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

Correct Answer: D - Single processor vs multiprocessor configuration

Minimum mode is for single processor, maximum mode is for multiprocessor systems with additional control signals.

Correct Answer: D - Primary register for arithmetic/logic operations

The accumulator (A register) is the primary register for ALU operations in 8085, storing one operand and the result.

Correct Answer: C - 64 KB

With 16-bit address bus, 8085 can address 2¹⁶ = 65,536 bytes = 64 KB of memory.

Correct Answer: D - 1 MB

With 20-bit address bus, 8086 can address 2²⁰ = 1,048,576 bytes = 1 MB of memory.

Correct Answer: B - BX, SI, DI, BP

BX (Base), SI (Source Index), DI (Destination Index), and BP (Base Pointer) can be used for memory addressing.

Correct Answer: C - Set Interrupt Mask

SIM (Set Interrupt Mask) is used to mask/unmask RST interrupts and control serial output in 8085.

Correct Answer: D - Read Interrupt Mask

RIM (Read Interrupt Mask) reads the status of interrupt masks and serial input in 8085.

Correct Answer: B - BIU fetches while EU executes

8086 uses pipelining where BIU fetches next instruction while EU executes current instruction simultaneously.

Correct Answer: A - 8085 is 8-bit while 8086 is 16-bit with segmented memory

8085 is an 8-bit processor with 64KB memory, while 8086 is 16-bit with 1MB memory using segmented addressing.

Correct Answer: B - 16

The 8085 has 16 address lines (A0–A15), allowing it to address 2¹⁶ = 64 KB of memory.

Correct Answer: C - ALE

ALE (Address Latch Enable) is a control signal used to demultiplex AD0–AD7 by latching the lower-order address into an external latch (typically 74LS373).

Correct Answer: B - Address and data share the same 8 pins

AD0–AD7 are multiplexed to carry the lower 8 bits of address during T1 state and data during subsequent T-states, reducing the total pin count.

Correct Answer: B - Non-maskable, edge and level triggered interrupt

TRAP is the highest priority interrupt in 8085. It is non-maskable and is both edge and level triggered, making it useful for critical events like power failure.

Correct Answer: C - 6

The 8085 has six 8-bit general-purpose registers: B, C, D, E, H, and L. They can also be used as three 16-bit register pairs: BC, DE, and HL.

Correct Answer: B - 16

The 8086 has a 16-bit data bus, allowing it to transfer 16 bits of data in a single bus cycle, unlike the 8085 which has an 8-bit data bus.

Correct Answer: B - 1 MB

With 20 address lines, the 8086 can address 2²⁰ = 1,048,576 bytes = 1 MB of memory.

Correct Answer: C - Bus Interface Unit (BIU)

The BIU (Bus Interface Unit) handles all bus operations including instruction fetching, memory read/write, and I/O operations. It also contains the instruction queue.

Correct Answer: A - 6 bytes

The 8086 has a 6-byte instruction queue (prefetch queue). The BIU fetches instructions ahead of time and stores them in this queue for the EU to execute, enabling pipelining.

Correct Answer: A - Segment × 16 + Offset

Physical Address = Segment Register × 16 (shift left by 4 bits) + Offset. This allows the 8086 to generate a 20-bit address from two 16-bit values.

Correct Answer: A - Zero flag

The Zero flag (Z) is set to 1 when the result of an arithmetic or logical operation is zero. It is reset to 0 when the result is non-zero.

Correct Answer: A - 3.072 MHz

The standard 8085 operates at 3.072 MHz. It internally divides the crystal frequency by 2, so an external crystal of 6.144 MHz is typically used.

Correct Answer: C - 16

The Stack Pointer in the 8085 is a 16-bit register that holds the address of the top of the stack. It can address any location in the 64 KB memory space.

Correct Answer: D - General Segment (GS)

The 8086 has four segment registers: CS, DS, SS, and ES (Extra Segment). GS was introduced later in the 80386 processor.

Correct Answer: C - Serial data communication

SID (Serial Input Data) and SOD (Serial Output Data) pins are used for serial communication in the 8085. SIM and RIM instructions are used to access these pins.

Correct Answer: C - I/O operation

When IO/M' is HIGH, it indicates an I/O operation (IN or OUT instruction). When LOW, it indicates a memory operation (read/write to memory).

Correct Answer: D - Minimum and Maximum

The 8086 operates in Minimum mode (single processor, MN/MX' pin HIGH) and Maximum mode (multiprocessor, MN/MX' pin LOW). The mode determines how bus control signals are generated.

Correct Answer: D - 5

The 8085 has 5 flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY). These are part of the flag register.

Correct Answer: A - 8

The Accumulator (A register) is an 8-bit register used for arithmetic and logical operations. It is the most frequently used register in the 8085.

Correct Answer: D - 0038H

RST 7 has a restart address of 0038H. The restart address is calculated as RST n × 8. So RST 7 = 7 × 8 = 56 = 38H.

Correct Answer: A - HL pair

The HL register pair is used as a memory pointer. In instructions like MOV A, M, the 'M' refers to the memory location pointed to by the HL register pair.

Correct Answer: A - CX

CX (Count Register) is used as the default counter for LOOP, REP, and other repetition instructions in the 8086.

Correct Answer: A - Resets the processor and sets PC to 0000H

RESET IN is an active-low input that resets the 8085 processor. After reset, the Program Counter is set to 0000H, and the processor begins executing from that address.

Correct Answer: B - Effective address (offset)

The BIU calculates the physical address by shifting the segment register left by 4 bits and adding the effective address (offset). The offset can come from IP, SP, BX, SI, DI, or a combination.

Correct Answer: D - 4

An opcode fetch machine cycle in the 8085 requires 4 T-states (T1 to T4). During T1, the address is placed on the bus; during T2 and T3, data is read; T4 is used for internal operations.