Sequential Circuits — Practice MCQs for CCAT

Correct Answer: B — 1-bit memory element

Flip-flop stores 1 bit of information.

Correct Answer: D — S=1, R=1

S=R=1 is invalid in SR flip-flop (indeterminate output).

Correct Answer: B — No invalid state (J=K=1 toggles)

JK: when J=K=1, output toggles (no invalid state).

Correct Answer: B — Output follows D input on clock

D flip-flop: Q follows D on clock edge (data latch).

Correct Answer: B — Output toggles

T=1: output toggles. T=0: output holds.

Correct Answer: B — Group of flip-flops storing multi-bit data

Register: group of flip-flops storing n-bit word.

Correct Answer: B — Sequential circuit that counts pulses

Counter: sequential circuit that counts clock pulses.

Correct Answer: B — 0 to 9

Mod-10 (decade) counter: 0 to 9 then resets.

Correct Answer: B — All flip-flops triggered simultaneously

Synchronous: all flip-flops share common clock.

Correct Answer: B — Shift data left/right, serial-parallel conversion

Shift register shifts data and converts serial↔parallel.

Correct Answer: B — Sequential circuits have memory/feedback

Sequential circuits have memory elements (flip-flops) and feedback, so output depends on current input and previous state.

Correct Answer: B — A level-triggered storage element

A latch is a level-triggered bistable device that can store one bit of data. It responds to input level, not edge.

Correct Answer: B — Edge-triggered storage element

A flip-flop is an edge-triggered bistable device that changes state only on clock edge (rising or falling).

Correct Answer: A — Uses only one input that goes to S, and its complement to R

D flip-flop has single data input D. S=D and R=D', so S and R can never both be 1 simultaneously.

Correct Answer: B — Copies input D to output Q

D flip-flop copies the value of D input to Q output on the active clock edge.

Correct Answer: D — J=1, K=1

When J=1 and K=1, JK flip-flop toggles its output on each clock edge (Q changes to Q').

Correct Answer: A — Counter where all flip-flops are clocked simultaneously

In synchronous counter, all flip-flops receive the same clock signal and change state simultaneously.

Correct Answer: B — Asynchronous counter where each flip-flop triggers the next

In ripple (asynchronous) counter, each flip-flop output clocks the next, causing changes to ripple through.

Correct Answer: C — 16

MOD (modulus) = 2^n where n is number of flip-flops. 4 flip-flops give MOD-16 counter (counts 0-15).

Correct Answer: A — Serial In Serial Out

SISO is Serial In Serial Out - data enters serially one bit at a time and exits serially.

Correct Answer: B — Shift register with output fed back to input

A ring counter is a shift register where the output of the last flip-flop is connected back to the input of the first.

Correct Answer: B — Ring counter with inverted feedback

A Johnson counter (twisted ring counter) has the inverted output of the last flip-flop connected to input of the first.

Correct Answer: A — Two flip-flops in series triggered on opposite clock edges

Master-slave consists of two flip-flops: master captures input on one clock edge, slave transfers to output on other edge.

Correct Answer: B — Unpredictable output due to multiple state changes in one clock

Race condition occurs when output changes multiple times during one clock period due to feedback, causing unpredictable results.

Correct Answer: B — Unstable intermediate state when setup/hold times violated

Metastability is an unstable state when input changes too close to clock edge, violating setup/hold times.