Sequential Circuits - Practice MCQs for CCAT

Correct Answer: C - 1-bit memory element

Flip-flop stores 1 bit of information.

Correct Answer: D - S=1, R=1

S=R=1 is invalid in SR flip-flop (indeterminate output).

Correct Answer: C - No invalid state (J=K=1 toggles)

JK: when J=K=1, output toggles (no invalid state).

Correct Answer: B - Output follows D input on clock

D flip-flop: Q follows D on clock edge (data latch).

Correct Answer: D - Output toggles

T=1: output toggles. T=0: output holds.

Correct Answer: B - Group of flip-flops storing multi-bit data

Register: group of flip-flops storing n-bit word.

Correct Answer: C - Sequential circuit that counts pulses

Counter: sequential circuit that counts clock pulses.

Correct Answer: B - 0 to 9

Mod-10 (decade) counter: 0 to 9 then resets.

Correct Answer: D - All flip-flops triggered simultaneously

Synchronous: all flip-flops share common clock.

Correct Answer: B - Shift data left/right, serial-parallel conversion

Shift register shifts data and converts serial<->parallel.

Correct Answer: D - Sequential circuits have memory/feedback

Sequential circuits have memory elements (flip-flops) and feedback, so output depends on current input and previous state.

Correct Answer: B - A level-triggered storage element

A latch is a level-triggered bistable device that can store one bit of data. It responds to input level, not edge.

Correct Answer: C - Edge-triggered storage element

A flip-flop is an edge-triggered bistable device that changes state only on clock edge (rising or falling).

Correct Answer: B - Uses only one input that goes to S, and its complement to R

D flip-flop has single data input D. S=D and R=D', so S and R can never both be 1 simultaneously.

Correct Answer: D - Copies input D to output Q

D flip-flop copies the value of D input to Q output on the active clock edge.

Correct Answer: A - J=1, K=1

When J=1 and K=1, JK flip-flop toggles its output on each clock edge (Q changes to Q').

Correct Answer: D - Counter where all flip-flops are clocked simultaneously

In synchronous counter, all flip-flops receive the same clock signal and change state simultaneously.

Correct Answer: D - Asynchronous counter where each flip-flop triggers the next

In ripple (asynchronous) counter, each flip-flop output clocks the next, causing changes to ripple through.

Correct Answer: B - 16

MOD (modulus) = 2ⁿ where n is number of flip-flops. 4 flip-flops give MOD-16 counter (counts 0-15).

Correct Answer: A - Serial In Serial Out

SISO is Serial In Serial Out - data enters serially one bit at a time and exits serially.

Correct Answer: A - Shift register with output fed back to input

A ring counter is a shift register where the output of the last flip-flop is connected back to the input of the first.

Correct Answer: A - Ring counter with inverted feedback

A Johnson counter (twisted ring counter) has the inverted output of the last flip-flop connected to input of the first.

Correct Answer: C - Two flip-flops in series triggered on opposite clock edges

Master-slave consists of two flip-flops: master captures input on one clock edge, slave transfers to output on other edge.

Correct Answer: B - Unpredictable output due to multiple state changes in one clock

Race condition occurs when output changes multiple times during one clock period due to feedback, causing unpredictable results.

Correct Answer: D - Unstable intermediate state when setup/hold times violated

Metastability is an unstable state when input changes too close to clock edge, violating setup/hold times.

Correct Answer: C - Sequential circuits have memory/feedback

Sequential circuits have memory elements (flip-flops/latches) that store state. Their output depends on both current inputs and the stored state (history), unlike combinational circuits whose output depends only on current inputs.

Correct Answer: C - S = 1, R = 1

In an SR latch using NOR gates, S = 1 and R = 1 is the forbidden state because it forces both outputs Q and Q' to 0, which violates the requirement that Q and Q' must be complementary.

Correct Answer: A - On the active clock edge

A D flip-flop captures the value of its D input on the active clock edge (rising or falling edge depending on design). The output Q takes the value of D at the triggering edge and holds it until the next active edge.

Correct Answer: D - 4

A mod-N counter requires ⌈log₂(N)⌉ flip-flops. For mod-16: ⌈log₂(16)⌉ = 4 flip-flops, which can represent states 0 through 15 (16 states).

Correct Answer: A - Q(n+1) = JQ' + K'Q

The characteristic equation of a JK flip-flop is Q(n+1) = JQ' + K'Q. When J=K=1, the flip-flop toggles; when J=K=0, it holds its state; J=1,K=0 sets; J=0,K=1 resets.

Correct Answer: A - T = 1 and clock edge occurs

A T (Toggle) flip-flop toggles its output (Q becomes Q') when T = 1 at the active clock edge. When T = 0, the output remains unchanged.

Correct Answer: D - In synchronous counters, all flip-flops are clocked simultaneously

In a synchronous counter, all flip-flops receive the same clock signal simultaneously. In an asynchronous (ripple) counter, the output of one flip-flop drives the clock of the next, causing propagation delay.

Correct Answer: D - 4

A 4-bit ring counter has exactly 4 distinct states. A single 1 (or 0) circulates through the 4 flip-flops: 1000 → 0100 → 0010 → 0001 → 1000. The number of states equals the number of flip-flops.

Correct Answer: A - 8

A Johnson (twisted ring) counter with n flip-flops has 2n valid states. For 4 flip-flops: 2 × 4 = 8 states. The sequence is: 0000→1000→1100→1110→1111→0111→0011→0001→0000.

Correct Answer: B - To asynchronously set or reset the flip-flop regardless of clock

Preset (PRE) and Clear (CLR) are asynchronous inputs that can set (Q=1) or reset (Q=0) the flip-flop immediately, regardless of the clock and other inputs. They are used for initialization.

Correct Answer: C - On the falling edge of clock

In a master-slave configuration, the master latch captures data when the clock is HIGH, and the slave latch captures (and outputs) data on the falling edge (when clock goes LOW). This eliminates the race condition.

Correct Answer: C - Bidirectional shift register

A bidirectional shift register can shift data both left and right based on a direction control input. A universal shift register supports all modes: shift left, shift right, parallel load, and hold.

Correct Answer: C - BCD counter

A BCD counter counts from 0 to 9 (0000 to 1001) and then resets to 0, which is a non-standard (truncated) binary sequence. It skips states 10-15 (1010-1111).

Correct Answer: C - Time data must be stable before the clock edge

Setup time is the minimum time the data input must be stable BEFORE the active clock edge for the flip-flop to correctly capture the data. Violating setup time can cause metastability.

Correct Answer: B - Minimum time data must remain stable after the clock edge

Hold time is the minimum time the data input must remain stable AFTER the active clock edge. Violating hold time can cause the flip-flop to capture incorrect data or become metastable.

Correct Answer: B - Cumulative propagation delay through flip-flops

In a ripple counter, each flip-flop triggers the next, causing cumulative propagation delays. For n flip-flops, the total delay is n × (propagation delay per flip-flop), limiting the maximum counting speed.

Correct Answer: A - Mealy outputs depend on both current state and inputs

In a Mealy machine, outputs depend on both the current state AND the current inputs. In a Moore machine, outputs depend only on the current state. Mealy machines may use fewer states but outputs can change asynchronously.

Correct Answer: D - An unpredictable state when setup/hold times are violated

Metastability is an unstable equilibrium state where the flip-flop output oscillates or remains at an intermediate voltage level. It occurs when setup or hold time is violated, and the flip-flop cannot resolve to a stable 0 or 1.

Correct Answer: A - 4

In a SISO shift register, data enters and exits one bit at a time. After loading 4 bits (4 clock pulses to load), it takes 4 more clock pulses to shift all bits out serially.

Correct Answer: B - Number of distinct states in the counting sequence

The modulus (mod) of a counter is the total number of distinct states in its counting sequence. A mod-N counter counts through N unique states before repeating.

Correct Answer: A - By detecting state 6 and resetting to 0

A mod-6 counter is created from a 3-bit counter by adding feedback logic that detects when the count reaches 6 (110) and forces the counter to reset to 0. This truncates the sequence to 0-5.

Correct Answer: A - Circles represent states, arrows represent transitions

In a state diagram (state transition diagram), circles represent the states of the sequential circuit, and arrows (directed edges) represent transitions between states, labeled with the input conditions and possibly outputs.

Correct Answer: A - Delay from clock edge to stable output

Clock-to-Q delay (tCQ) is the time from the active clock edge to when the output Q becomes stable at its new value. It is a key parameter for determining the maximum clock frequency of sequential circuits.

Correct Answer: B - Shift left, shift right, parallel load, and hold

A universal shift register supports four operations: shift left, shift right, parallel load (all bits loaded simultaneously), and hold (maintain current state). Mode select inputs choose the operation.

Correct Answer: C - Current state, inputs, next state, and outputs

A state table (transition table) lists all combinations of current state and inputs, along with the corresponding next state and outputs. It provides a complete tabular description of the sequential circuit's behavior.