Combinational Circuits - Practice MCQs for CCAT

Correct Answer: B - 2 inputs, 2 outputs (Sum, Carry)

Half adder: 2 inputs (A, B), 2 outputs (Sum, Carry).

Correct Answer: C - 3 inputs (A, B, Cin)

Full adder: 3 inputs (A, B, Carry-in), 2 outputs (Sum, Carry-out).

Correct Answer: C - Many inputs, one output (data selector)

MUX: selects one of many inputs to single output.

Correct Answer: B - One input to many outputs

DEMUX: routes one input to one of many outputs.

Correct Answer: C - 2ⁿ outputs

n-to-2ⁿ decoder: n inputs produce 2ⁿ outputs.

Correct Answer: A - 2ⁿ inputs to n-bit output

Encoder: 2ⁿ inputs to n-bit binary output.

Correct Answer: B - Gives priority to highest input

Priority encoder gives precedence to highest-order active input.

Correct Answer: D - 2

2ⁿ inputs need n select lines. 4 = 2², so 2 select lines.

Correct Answer: D - Magnitude (A>B, A<B, A=B)

Magnitude comparator compares A>B, A<B, A=B.

Correct Answer: C - 7 segments for display

Converts BCD to signals for 7-segment display.

Correct Answer: B - 3

An 8:1 MUX needs 3 select lines because 2³ = 8 possible input selections.

Correct Answer: A - 8

A 3-to-8 decoder has 3 inputs and 8 outputs (2³ = 8 possible output combinations).

Correct Answer: A - Encoder that outputs code for highest priority active input

A priority encoder outputs the binary code of the highest priority active input when multiple inputs are active.

Correct Answer: A - Sum and Carry

A half adder produces two outputs: Sum (A XOR B) and Carry (A AND B).

Correct Answer: B - 2

A full adder can be constructed using 2 half adders and an OR gate for the carry output.

Correct Answer: C - A>B, A<B, A=B

A magnitude comparator typically has three outputs: A>B, A<B, and A=B.

Correct Answer: B - Time for carry to ripple through all stages of adder

Carry propagation delay is the time for carry signal to propagate through all bit positions in a ripple carry adder.

Correct Answer: D - Adder that predicts carries in advance to reduce delay

Carry lookahead adder calculates carry signals in advance using generate and propagate logic, reducing propagation delay.

Correct Answer: B - Generates parity bit for error detection

A parity generator produces an additional bit (parity bit) to make the total number of 1s either even or odd.

Correct Answer: D - Circuit that performs binary subtraction

A subtractor performs binary subtraction. A half subtractor has Difference and Borrow outputs.

Correct Answer: C - Converting one code to another (e.g., BCD to Excess-3)

Code converters transform data from one binary code representation to another.

Correct Answer: C - Combinational circuit that shifts data by any amount in one cycle

A barrel shifter can shift or rotate data by any number of positions in a single clock cycle using multiplexers.

Correct Answer: C - Combinational logic circuit (lookup table)

ROM can implement any combinational function as a lookup table by storing truth table values.

Correct Answer: D - Programmable Logic Array

PLA (Programmable Logic Array) has programmable AND and OR arrays for implementing combinational logic.

Correct Answer: A - Programmable Array Logic

PAL (Programmable Array Logic) has programmable AND array and fixed OR array.

Correct Answer: A - 2

A 2ⁿ:1 multiplexer requires n select lines. For a 4:1 MUX: 4 = 2², so 2 select lines are needed to select one of the 4 inputs.

Correct Answer: C - Code converter

A code converter is a combinational circuit that converts data from one code to another. Binary to Gray code conversion uses XOR gates: Gi = Bi ⊕ Bi+1.

Correct Answer: A - 8

A 3-to-8 decoder has 3 input lines and 2³ = 8 output lines. For each input combination, exactly one of the 8 outputs is activated.

Correct Answer: D - 2 inputs, 2 outputs

A half adder has 2 inputs (A and B) and 2 outputs: Sum (S = A ⊕ B) and Carry (C = A · B). It adds two single bits without considering carry input.

Correct Answer: D - Full adder has a carry input

A full adder has 3 inputs (A, B, and Carry-in) while a half adder has only 2 inputs (A, B). The carry input allows full adders to be cascaded for multi-bit addition.

Correct Answer: B - 3

An 8:1 MUX has 3 select lines and can implement any 3-variable Boolean function by connecting appropriate constants (0 or 1) or input variables to the data inputs.

Correct Answer: B - Handles multiple active inputs by prioritizing the highest

A priority encoder handles the case when multiple inputs are active simultaneously by giving priority to the highest-order active input and encoding its position.

Correct Answer: C - 4

A 4-bit binary adder (ripple carry adder) requires 4 full adders, one for each bit position. The carry output of each full adder connects to the carry input of the next.

Correct Answer: D - Routes a single input to one of many outputs

A demultiplexer (DEMUX) takes a single data input and routes it to one of several output lines based on the select inputs. It performs the reverse of a multiplexer.

Correct Answer: D - 3

A magnitude comparator has 3 outputs: A > B, A = B, and A < B. These three conditions cover all possible magnitude relationships between two numbers.

Correct Answer: B - AB + (A ⊕ B)Cin

The carry output of a full adder: Cout = AB + (A ⊕ B)Cin. This can also be written as Cout = AB + BCin + ACin, meaning carry is generated when any two or more inputs are 1.

Correct Answer: A - Seven-segment LED display

A BCD to 7-segment decoder converts a 4-bit BCD input (0-9) to the appropriate 7-segment output pattern to display the corresponding decimal digit on a 7-segment LED display.

Correct Answer: B - Ai · Bi

The generate function Gi = Ai · Bi indicates that a carry is generated at position i regardless of the incoming carry. A carry is generated when both inputs at that position are 1.

Correct Answer: B - Pi = Ai ⊕ Bi

The propagate function Pi = Ai ⊕ Bi indicates that position i will propagate an incoming carry to the next position. If Pi = 1, the carry-in will pass through.

Correct Answer: A - 2

A 1-to-2ⁿ demultiplexer requires n select lines. For 1-to-4 DEMUX: 4 = 2², so 2 select lines are needed to route the input to one of 4 outputs.

Correct Answer: C - Decoder with enable input

A decoder with an enable input can function as a demultiplexer. The enable input serves as the data input, and the select lines choose which output receives the data.

Correct Answer: C - Slow due to carry propagation delay

In a ripple carry adder, each full adder must wait for the carry from the previous stage. This serial carry propagation causes significant delay, especially for larger bit widths.

Correct Answer: D - 4

An 8-to-3 encoder produces 3 output bits for encoding. With a valid output indicator (V), there are 4 total outputs: 3 encoded bits + 1 valid bit that indicates if any input is active.

Correct Answer: A - Complementing the subtrahend and adding 1 (2's complement method)

Subtraction A - B is performed as A + B' + 1 (2's complement). The subtrahend B is complemented using inverters, and the initial carry-in is set to 1.

Correct Answer: A - A parity bit to make total number of 1s even or odd

A parity generator generates an extra bit (parity bit) appended to data to make the total number of 1s either even (even parity) or odd (odd parity) for error detection.

Correct Answer: A - G and P values of all 4 bits and C0

In CLA, C4 is computed using: C4 = G3 + P3·G2 + P3·P2·G1 + P3·P2·P1·G0 + P3·P2·P1·P0·C0. All carries are computed simultaneously from generate, propagate, and initial carry.

Correct Answer: D - Data selector

A multiplexer is also called a data selector because it selects one of several input data lines and routes it to a single output line based on the select inputs.

Correct Answer: A - Connect variables to select lines and function values to data inputs

To implement a 2-variable function using a 4:1 MUX: Connect the 2 variables to the select lines (S1, S0), and connect the function output values (0 or 1) for each minterm to the corresponding data inputs.

Correct Answer: D - A momentary unwanted output glitch during input transition

A hazard is a temporary unwanted output change (glitch) that occurs when inputs change, caused by different propagation delays through different paths of the circuit. Types include static and dynamic hazards.

Correct Answer: B - A ⊕ B ⊕ Cin

The sum output of a full adder is S = A ⊕ B ⊕ Cin (XOR of all three inputs). The sum is 1 when an odd number of inputs are 1.