Combinational Circuits — Practice MCQs for CCAT

Correct Answer: C — 2 inputs, 2 outputs (Sum, Carry)

Half adder: 2 inputs (A, B), 2 outputs (Sum, Carry).

Correct Answer: B — 3 inputs (A, B, Cin)

Full adder: 3 inputs (A, B, Carry-in), 2 outputs (Sum, Carry-out).

Correct Answer: B — Many inputs, one output (data selector)

MUX: selects one of many inputs to single output.

Correct Answer: B — One input to many outputs

DEMUX: routes one input to one of many outputs.

Correct Answer: B — 2^n outputs

n-to-2^n decoder: n inputs produce 2^n outputs.

Correct Answer: B — 2^n inputs to n-bit output

Encoder: 2^n inputs to n-bit binary output.

Correct Answer: B — Gives priority to highest input

Priority encoder gives precedence to highest-order active input.

Correct Answer: B — 2

2^n inputs need n select lines. 4 = 2², so 2 select lines.

Correct Answer: B — Magnitude (A>B, A<B, A=B)

Magnitude comparator compares A>B, A<B, A=B.

Correct Answer: B — 7 segments for display

Converts BCD to signals for 7-segment display.

Correct Answer: B — 3

An 8:1 MUX needs 3 select lines because 2³ = 8 possible input selections.

Correct Answer: B — 8

A 3-to-8 decoder has 3 inputs and 8 outputs (2³ = 8 possible output combinations).

Correct Answer: B — Encoder that outputs code for highest priority active input

A priority encoder outputs the binary code of the highest priority active input when multiple inputs are active.

Correct Answer: C — Sum and Carry

A half adder produces two outputs: Sum (A XOR B) and Carry (A AND B).

Correct Answer: B — 2

A full adder can be constructed using 2 half adders and an OR gate for the carry output.

Correct Answer: B — A>B, A<B, A=B

A magnitude comparator typically has three outputs: A>B, A<B, and A=B.

Correct Answer: B — Time for carry to ripple through all stages of adder

Carry propagation delay is the time for carry signal to propagate through all bit positions in a ripple carry adder.

Correct Answer: A — Adder that predicts carries in advance to reduce delay

Carry lookahead adder calculates carry signals in advance using generate and propagate logic, reducing propagation delay.

Correct Answer: B — Generates parity bit for error detection

A parity generator produces an additional bit (parity bit) to make the total number of 1s either even or odd.

Correct Answer: B — Circuit that performs binary subtraction

A subtractor performs binary subtraction. A half subtractor has Difference and Borrow outputs.

Correct Answer: B — Converting one code to another (e.g., BCD to Excess-3)

Code converters transform data from one binary code representation to another.

Correct Answer: B — Combinational circuit that shifts data by any amount in one cycle

A barrel shifter can shift or rotate data by any number of positions in a single clock cycle using multiplexers.

Correct Answer: B — Combinational logic circuit (lookup table)

ROM can implement any combinational function as a lookup table by storing truth table values.

Correct Answer: A — Programmable Logic Array

PLA (Programmable Logic Array) has programmable AND and OR arrays for implementing combinational logic.

Correct Answer: A — Programmable Array Logic

PAL (Programmable Array Logic) has programmable AND array and fixed OR array.