Memory Systems - Practice MCQs for CCAT

Correct Answer: B - Register

Hierarchy: Registers > Cache > RAM > SSD/HDD.

Correct Answer: D - Between CPU and RAM

Cache is between CPU and main memory for faster access.

Correct Answer: A - Data found in cache

Cache hit: requested data is found in cache.

Correct Answer: D - Locality of reference

Cache exploits temporal and spatial locality of reference.

Correct Answer: B - Block can go anywhere

Fully associative: any block can be in any cache line.

Correct Answer: A - Block has one fixed location

Direct mapped: each block has exactly one possible cache location.

Correct Answer: A - Writes to cache and memory simultaneously

Write-through updates both cache and main memory on every write.

Correct Answer: B - Writes to cache, updates memory later

Write-back: writes to cache, updates memory only when evicted.

Correct Answer: D - SRAM is faster, no refresh needed

SRAM is faster and doesn't need refresh; used for cache. DRAM needs refresh.

Correct Answer: D - Non-volatile

ROM (Read Only Memory) is non-volatile - retains data without power.

Correct Answer: C - Registers

Registers are located within the CPU and have the fastest access time, typically less than 1 nanosecond.

Correct Answer: C - Programs tend to access the same or nearby memory locations repeatedly

Locality principle states that programs tend to access the same data (temporal locality) or nearby data (spatial locality) repeatedly.

Correct Answer: B - DRAM

DRAM (Dynamic RAM) stores data in capacitors that leak charge, requiring periodic refresh to maintain data.

Correct Answer: B - Translate virtual addresses to physical addresses

The MMU translates virtual addresses used by programs to physical addresses in actual memory.

Correct Answer: D - In one specific cache line only

In direct-mapped cache, each memory block can only go to one specific cache line determined by its address.

Correct Answer: A - Least Recently Used

LRU (Least Recently Used) replaces the cache block that has not been accessed for the longest time.

Correct Answer: C - Using hard disk space as an extension of RAM

Virtual memory uses secondary storage (hard disk) to extend the apparent size of physical RAM.

Correct Answer: A - Required page is not in physical memory

A page fault occurs when a program accesses a page that is not currently in physical memory, requiring it to be loaded from disk.

Correct Answer: B - Registers > Cache > RAM > Hard Disk

The memory hierarchy from fastest to slowest is: Registers > Cache > RAM > Hard Disk/SSD.

Correct Answer: A - Indicates the cache line has been modified and differs from main memory

The dirty bit indicates that the cache line has been modified (written to) and needs to be written back to main memory before replacement.

Correct Answer: C - Combination of direct and associative - cache divided into sets

Set-associative cache divides cache into sets, where a block maps to a specific set but can go in any line within that set.

Correct Answer: C - Time taken to load data from main memory on a miss

Cache miss penalty is the additional time required to fetch data from main memory when data is not found in cache.

Correct Answer: B - Electrically Erasable Programmable ROM

EEPROM is Electrically Erasable Programmable ROM - can be erased and reprogrammed using electrical signals.

Correct Answer: D - Recently accessed data is likely to be accessed again soon

Temporal locality means that data that has been recently accessed is likely to be accessed again in the near future.

Correct Answer: D - Data near recently accessed locations is likely to be accessed soon

Spatial locality means that if a memory location is accessed, nearby memory locations are likely to be accessed soon.

Correct Answer: A - L1 cache

L1 cache is the fastest and smallest cache, located closest to the CPU core. It typically has a size of 32KB-64KB and access time of 1-2 clock cycles.

Correct Answer: A - When requested data is found in cache

A cache hit occurs when the CPU requests data and that data is found in the cache memory, allowing for faster access compared to fetching from main memory.

Correct Answer: D - Secondary storage (Hard disk)

The memory hierarchy from smallest to largest capacity is: Registers → Cache → Main Memory (RAM) → Secondary Storage. Secondary storage (hard disks, SSDs) has the largest capacity but slowest access time.

Correct Answer: D - Cache memory

SRAM is used for cache memory because it is faster than DRAM (no refresh needed), though it is more expensive and has lower density. Each SRAM cell uses 6 transistors.

Correct Answer: B - DRAM needs periodic refresh while SRAM does not

DRAM stores data as charge in capacitors which leak over time, requiring periodic refresh. SRAM uses flip-flops to store data and does not need refresh, making it faster but more expensive.

Correct Answer: B - Exactly one specific cache line

In a direct-mapped cache, each memory block can only be placed in one specific cache line, determined by (block address) mod (number of cache lines). This is simple but can cause conflicts.

Correct Answer: B - Fully associative mapping

In fully associative mapping, a memory block can be placed in any cache line. This provides the most flexibility and lowest conflict miss rate but requires comparing the tag with all cache entries.

Correct Answer: D - 0.90

Hit ratio = Number of cache hits / Total memory accesses = 90/100 = 0.90 or 90%. This means 90% of memory accesses are satisfied by the cache.

Correct Answer: C - Higher data transfer rates and lower voltage

DDR4 offers higher data transfer rates (up to 3200 MT/s vs 2133 MT/s for DDR3), lower voltage (1.2V vs 1.5V for DDR3), and higher density modules compared to DDR3.

Correct Answer: B - Programs larger than physical memory to execute

Virtual memory uses secondary storage (disk) as an extension of main memory, allowing programs larger than the available physical RAM to execute by swapping pages between RAM and disk.

Correct Answer: C - When a requested page is not in physical memory

A page fault occurs when a program accesses a virtual page that is not currently loaded in physical memory (RAM). The OS must then load the required page from secondary storage.

Correct Answer: B - LRU (Least Recently Used)

LRU (Least Recently Used) replacement policy evicts the cache block that has not been accessed for the longest period of time, based on the principle of temporal locality.

Correct Answer: A - Hit ratio, cache access time, and main memory access time

Effective access time = (Hit ratio × Cache access time) + (Miss ratio × Main memory access time). All three factors determine the average time to access data.

Correct Answer: C - Non-volatile memory

ROM is non-volatile memory that retains its contents even when power is turned off. It is used to store firmware, BIOS, and other permanent data.

Correct Answer: A - 2 cache lines

In a 2-way set-associative cache, each set contains 2 cache lines. A memory block maps to a specific set but can be placed in either of the 2 lines within that set.

Correct Answer: C - To cache page table entries for faster virtual-to-physical address translation

The TLB is a specialized cache that stores recent virtual-to-physical page address translations. It speeds up memory access by avoiding repeated page table lookups in main memory.

Correct Answer: C - Flash memory (EEPROM)

Modern computers use Flash memory (a type of EEPROM) to store BIOS/UEFI firmware, as it is non-volatile and can be electrically erased and reprogrammed for firmware updates.

Correct Answer: D - Accessing memory locations near recently accessed locations

Spatial locality means that if a memory location is accessed, nearby memory locations are likely to be accessed soon. This principle is exploited by fetching entire cache blocks/lines.

Correct Answer: A - Data is written only to cache and updated to main memory when the cache line is replaced

In write-back policy, data is written only to the cache. The modified cache line (dirty block) is written to main memory only when it is evicted/replaced, reducing memory bus traffic.

Correct Answer: B - Data is written to both cache and main memory simultaneously

In write-through policy, every write to cache is simultaneously written to main memory. This ensures consistency between cache and memory but generates more memory bus traffic.

Correct Answer: D - Error detection and correction capability

ECC (Error-Correcting Code) memory can detect and correct single-bit errors, and detect (but not correct) multi-bit errors. It is used in servers and critical systems for data integrity.

Correct Answer: A - Recently accessed locations are likely to be accessed again soon

Temporal locality means that if a memory location is accessed at one point in time, it is likely to be accessed again in the near future. This is exploited by keeping recently used data in cache.

Correct Answer: A - Register → Cache → RAM → Disk

The access time order from fastest to slowest is: Registers (< 1ns) → Cache (1-10ns) → RAM (50-100ns) → Disk (5-10ms). This matches the memory hierarchy.

Correct Answer: C - Dividing memory into modules that can be accessed in parallel

Memory interleaving divides memory into multiple modules (banks) and distributes consecutive addresses across them. This allows overlapping of access times, improving effective bandwidth.

Correct Answer: C - The additional time taken to fetch data from main memory when it is not in cache

Cache miss penalty is the extra time required to fetch the requested data from main memory (or a lower level cache) when it is not found in the cache, compared to a cache hit.