Computer Architecture

Memory Systems — Practice MCQs for CCAT

25 Questions Section C: Hardware Computer Architecture

Practice 25 Memory Systems multiple-choice questions designed for CDAC CCAT exam preparation. Click "Show Answer" to reveal the correct option with detailed explanation.

Q1.
Which memory is fastest?
ARAM
BCache
CHard Disk
DRegister
Show Answer & Explanation

Correct Answer: D — Register

Hierarchy: Registers > Cache > RAM > SSD/HDD.

Q2.
Cache memory is placed:
ABetween CPU and RAM
BAfter RAM
COn hard disk
DOutside computer
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Correct Answer: A — Between CPU and RAM

Cache is between CPU and main memory for faster access.

Q3.
Cache hit means:
AData not found
BData found in cache
CCache is full
DCache error
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Correct Answer: B — Data found in cache

Cache hit: requested data is found in cache.

Q4.
Principle behind cache is:
AData is random
BLocality of reference
CData is sequential
DMemory is unlimited
Show Answer & Explanation

Correct Answer: B — Locality of reference

Cache exploits temporal and spatial locality of reference.

Q5.
Associative mapping in cache:
ABlock can go anywhere
BBlock has fixed location
CUses sets
DNo mapping
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Correct Answer: A — Block can go anywhere

Fully associative: any block can be in any cache line.

Q6.
Direct mapping:
ABlock can go anywhere
BBlock has one fixed location
CUses sets
DIs most flexible
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Correct Answer: B — Block has one fixed location

Direct mapped: each block has exactly one possible cache location.

Q7.
Write-through cache policy:
AWrites only to cache
BWrites to cache and memory simultaneously
CWrites only to memory
DNever writes
Show Answer & Explanation

Correct Answer: B — Writes to cache and memory simultaneously

Write-through updates both cache and main memory on every write.

Q8.
Write-back cache policy:
AWrites to memory immediately
BWrites to cache, updates memory later
CNever caches writes
DDiscards writes
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Correct Answer: B — Writes to cache, updates memory later

Write-back: writes to cache, updates memory only when evicted.

Q9.
SRAM vs DRAM:
ASRAM needs refresh
BDRAM is faster
CSRAM is faster, no refresh needed
DSame speed
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Correct Answer: C — SRAM is faster, no refresh needed

SRAM is faster and doesn't need refresh; used for cache. DRAM needs refresh.

Q10.
ROM is:
AVolatile
BNon-volatile
CWritable
DTemporary storage
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Correct Answer: B — Non-volatile

ROM (Read Only Memory) is non-volatile - retains data without power.

Q11.
Which memory is closest to the CPU and has the fastest access time?
AMain Memory (RAM)
BCache Memory
CRegisters
DVirtual Memory
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Correct Answer: C — Registers

Registers are located within the CPU and have the fastest access time, typically less than 1 nanosecond.

Q12.
What is the principle of locality that cache memory exploits?
APrograms access random memory locations
BPrograms tend to access the same or nearby memory locations repeatedly
CPrograms always access memory sequentially
DPrograms access memory in fixed patterns
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Correct Answer: B — Programs tend to access the same or nearby memory locations repeatedly

Locality principle states that programs tend to access the same data (temporal locality) or nearby data (spatial locality) repeatedly.

Q13.
What type of RAM needs to be refreshed periodically?
ASRAM
BDRAM
CROM
DFlash Memory
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Correct Answer: B — DRAM

DRAM (Dynamic RAM) stores data in capacitors that leak charge, requiring periodic refresh to maintain data.

Q14.
What is the purpose of the Memory Management Unit (MMU)?
AIncrease memory speed
BTranslate virtual addresses to physical addresses
CCompress data in memory
DEncrypt memory contents
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Correct Answer: B — Translate virtual addresses to physical addresses

The MMU translates virtual addresses used by programs to physical addresses in actual memory.

Q15.
In a direct-mapped cache, where can a memory block be placed?
AIn any cache line
BIn one specific cache line only
CIn one of two possible lines
DRandomly in any line
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Correct Answer: B — In one specific cache line only

In direct-mapped cache, each memory block can only go to one specific cache line determined by its address.

Q16.
What is the cache replacement policy LRU?
ALast Recently Used
BLeast Recently Used
CLongest Running Update
DLatest Read Update
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Correct Answer: B — Least Recently Used

LRU (Least Recently Used) replaces the cache block that has not been accessed for the longest time.

Q17.
What is virtual memory?
AMemory in the cloud
BUsing hard disk space as an extension of RAM
CMemory inside the CPU
DEncrypted memory
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Correct Answer: B — Using hard disk space as an extension of RAM

Virtual memory uses secondary storage (hard disk) to extend the apparent size of physical RAM.

Q18.
What is a page fault?
AError in memory chip
BRequired page is not in physical memory
CMemory is full
DPage size mismatch
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Correct Answer: B — Required page is not in physical memory

A page fault occurs when a program accesses a page that is not currently in physical memory, requiring it to be loaded from disk.

Q19.
What is the typical hierarchy of memory from fastest to slowest?
ARAM > Cache > Registers > Hard Disk
BRegisters > Cache > RAM > Hard Disk
CCache > Registers > RAM > Hard Disk
DHard Disk > RAM > Cache > Registers
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Correct Answer: B — Registers > Cache > RAM > Hard Disk

The memory hierarchy from fastest to slowest is: Registers > Cache > RAM > Hard Disk/SSD.

Q20.
What is the purpose of the dirty bit in cache?
AIndicates the cache line is corrupted
BIndicates the cache line has been modified and differs from main memory
CIndicates the cache line is empty
DIndicates the cache line is locked
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Correct Answer: B — Indicates the cache line has been modified and differs from main memory

The dirty bit indicates that the cache line has been modified (written to) and needs to be written back to main memory before replacement.

Q21.
What is set-associative cache mapping?
ASame as direct mapping
BSame as fully associative
CCombination of direct and associative - cache divided into sets
DRandom mapping
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Correct Answer: C — Combination of direct and associative - cache divided into sets

Set-associative cache divides cache into sets, where a block maps to a specific set but can go in any line within that set.

Q22.
What is cache miss penalty?
ACost of cache hardware
BTime taken to load data from main memory on a miss
CNumber of cache misses
DCache line size
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Correct Answer: B — Time taken to load data from main memory on a miss

Cache miss penalty is the additional time required to fetch data from main memory when data is not found in cache.

Q23.
EEPROM stands for:
AElectronic Erasable Program ROM
BElectrically Erasable Programmable ROM
CExtended Enhanced Program ROM
DExternal Erasable Program ROM
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Correct Answer: B — Electrically Erasable Programmable ROM

EEPROM is Electrically Erasable Programmable ROM - can be erased and reprogrammed using electrical signals.

Q24.
What is temporal locality?
AAccessing nearby memory locations
BRecently accessed data is likely to be accessed again soon
CSequential memory access
DRandom memory access
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Correct Answer: B — Recently accessed data is likely to be accessed again soon

Temporal locality means that data that has been recently accessed is likely to be accessed again in the near future.

Q25.
What is spatial locality?
ARecently accessed data will be accessed again
BData near recently accessed locations is likely to be accessed soon
CTime-based memory access
DCPU location in memory
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Correct Answer: B — Data near recently accessed locations is likely to be accessed soon

Spatial locality means that if a memory location is accessed, nearby memory locations are likely to be accessed soon.