I/O Systems - Practice MCQs for CCAT

Correct Answer: D - CPU repeatedly checks device status

Polling: CPU continuously checks if device is ready.

Correct Answer: A - Device signals CPU when ready

Device interrupts CPU when it needs attention.

Correct Answer: C - Direct Memory Access

DMA = Direct Memory Access - transfers data without CPU.

Correct Answer: C - Frees CPU during data transfer

DMA frees CPU to do other work during large data transfers.

Correct Answer: B - I/O devices share memory address space

Memory-mapped I/O: devices accessed like memory locations.

Correct Answer: D - Uses separate I/O address space

Isolated I/O: separate address space with IN/OUT instructions.

Correct Answer: A - DMA

DMA is fastest for large data transfers without CPU involvement.

Correct Answer: D - Communication pathway

Bus is communication pathway between components.

Correct Answer: D - Unidirectional (CPU to memory)

Address bus is unidirectional - CPU sends addresses.

Correct Answer: B - Bidirectional

Data bus is bidirectional - data flows both ways.

Correct Answer: A - CPU continuously checks I/O device status

In programmed I/O, the CPU continuously polls the I/O device status register to check if the device is ready for data transfer.

Correct Answer: B - CPU time is wasted in polling

Programmed I/O wastes CPU cycles as the processor must continuously check device status instead of doing useful work.

Correct Answer: D - DMA Controller

The DMA Controller (DMAC) manages DMA operations, taking over the bus to transfer data between I/O devices and memory.

Correct Answer: A - DMA takes bus control from CPU for one bus cycle at a time

In cycle stealing, DMA controller takes control of the bus for one cycle at a time, interleaving with CPU bus operations.

Correct Answer: A - DMA transfers entire block of data before releasing bus

In burst mode, DMA controller takes control of bus and transfers entire data block before releasing the bus to CPU.

Correct Answer: D - Address used to communicate with I/O device

An I/O port is an address or set of addresses used by the CPU to communicate with a specific I/O device.

Correct Answer: C - Code that executes when an interrupt occurs

ISR is the code that is executed by CPU in response to an interrupt, handling the event that caused the interrupt.

Correct Answer: C - Time from interrupt request to start of ISR execution

Interrupt latency is the delay between when an interrupt is generated and when the ISR begins executing.

Correct Answer: B - Contains addresses of interrupt service routines

The Interrupt Vector Table stores the starting addresses (vectors) of ISRs for each interrupt type.

Correct Answer: D - Interrupt that can be disabled by software

A maskable interrupt can be disabled (masked) by software using the interrupt flag, preventing CPU from responding to it.

Correct Answer: B - Interrupt that cannot be disabled and must be serviced

NMI is a high-priority interrupt that cannot be disabled by software, used for critical events like power failure.

Correct Answer: C - Carrying control signals like read/write

The control bus carries control signals like read/write, clock, interrupt requests, and bus request signals.

Correct Answer: D - Control signal exchange between CPU and device for synchronization

Handshaking is the exchange of control signals between CPU and I/O device to coordinate data transfer timing.

Correct Answer: C - Process of deciding which device gets bus control when multiple devices request it

Bus arbitration determines which of multiple devices requesting bus access should be granted control of the bus.

Correct Answer: B - DMA that operates only when CPU is not using the bus

Transparent DMA transfers data only during cycles when CPU is not using the bus, appearing invisible to CPU operation.

Correct Answer: C - Continuously checks the status of the I/O device

In programmed I/O (also called polling), the CPU continuously checks (polls) the status of the I/O device to see if it is ready for data transfer. This keeps the CPU busy-waiting.

Correct Answer: B - CPU can perform other tasks while waiting for I/O

In interrupt-driven I/O, the CPU can execute other instructions while waiting for I/O. The I/O device sends an interrupt signal when ready, freeing the CPU from continuous polling.

Correct Answer: C - Data transfer between I/O devices and memory without CPU intervention

DMA allows I/O devices to transfer data directly to/from main memory without CPU involvement. The DMA controller handles the transfer, freeing the CPU to perform other tasks.

Correct Answer: D - DMA

DMA provides the highest data transfer rate because data is transferred directly between the I/O device and memory without CPU intervention, eliminating the CPU bottleneck.

Correct Answer: C - A shared communication pathway for data transfer between components

A bus is a shared set of wires (communication pathway) that connects various components of a computer (CPU, memory, I/O devices) and allows them to transfer data between each other.

Correct Answer: B - Data bus, Address bus, Control bus

The system bus consists of: Data bus (carries data), Address bus (carries memory addresses), and Control bus (carries control signals like read/write, interrupt, clock).

Correct Answer: C - The maximum addressable memory

The width of the address bus determines how many unique memory locations can be addressed. A 32-bit address bus can address 2³² = 4GB of memory.

Correct Answer: A - I/O devices share the same address space as memory

In memory-mapped I/O, I/O device registers are assigned addresses in the same address space as memory. The CPU uses the same instructions (load/store) for both memory and I/O operations.

Correct Answer: C - Have a separate address space with special I/O instructions

In isolated (port-mapped) I/O, I/O devices have a separate address space from memory and are accessed using special I/O instructions (IN/OUT) rather than memory load/store instructions.

Correct Answer: B - The DMA controller steals a bus cycle from the CPU to transfer data

In cycle stealing mode, the DMA controller takes control of the bus for one cycle at a time to transfer one word, then returns bus control to the CPU. This causes minimal CPU slowdown.

Correct Answer: A - Serial bus

USB is a serial bus standard that transmits data one bit at a time over a single data line. Despite being serial, modern USB versions (USB 3.0+) achieve very high data transfer rates.

Correct Answer: B - The method of determining which device gets control of the bus

Bus arbitration is the process of determining which device (bus master) gets control of the shared bus when multiple devices request access simultaneously.

Correct Answer: A - Devices closer to the arbiter have higher priority

In daisy chain arbitration, the bus grant signal passes through devices sequentially. Devices physically closer to the arbiter in the chain receive the grant first, giving them higher priority.

Correct Answer: B - To synchronize data transfer between devices using control signals

Handshaking uses control signals (request, acknowledge) to synchronize data transfer between two devices, ensuring the receiving device is ready before data is sent.

Correct Answer: A - Serial point-to-point communication

PCIe uses serial point-to-point links (lanes) rather than a shared parallel bus. Multiple lanes can be combined (x1, x4, x8, x16) for higher bandwidth.

Correct Answer: B - A specialized processor dedicated to managing I/O operations

An I/O processor (IOP) or channel is a specialized processor that handles I/O operations independently, further reducing the load on the main CPU compared to DMA.

Correct Answer: C - Takes control of the bus and transfers an entire block of data before releasing

In burst mode, the DMA controller takes exclusive control of the bus and transfers an entire block of data in one continuous burst before releasing the bus back to the CPU.

Correct Answer: D - The address of the interrupt service routine (ISR)

An interrupt vector is a memory address (or table entry) that points to the starting address of the interrupt service routine (ISR) associated with a specific interrupt.

Correct Answer: A - To temporarily store data during transfer between devices with different speeds

An I/O buffer temporarily holds data during transfer between devices that operate at different speeds, smoothing out the speed mismatch between fast CPU/memory and slow I/O devices.

Correct Answer: B - Can be disabled or ignored by the CPU using interrupt flags

Maskable interrupts can be enabled or disabled by the CPU through the interrupt mask flag. When masked (disabled), the CPU ignores these interrupts until they are unmasked.

Correct Answer: A - Critical events like hardware failures or power failure

Non-maskable interrupts cannot be disabled and are reserved for critical events like hardware failures, memory parity errors, or power failure that require immediate attention.

Correct Answer: A - It determines how many bits can be transferred in one bus cycle

The data bus width determines how many bits of data can be transferred simultaneously in one bus cycle. A 64-bit data bus can transfer 8 bytes at a time.

Correct Answer: A - SATA offers higher transfer rates with simpler cabling

SATA replaced PATA by using serial signaling which allows higher clock speeds, thinner cables, better airflow, and hot-swapping capability, despite using fewer data wires.

Correct Answer: D - To indicate the current state of the I/O device (ready, busy, error)

The status register in an I/O interface contains flags that indicate the current state of the device, such as ready/busy, data available, error condition, etc.

Correct Answer: D - The interrupt with the highest priority is serviced first

In a priority interrupt system, each interrupt source has an assigned priority level. When multiple interrupts occur simultaneously, the one with the highest priority is serviced first.