I/O Systems — Practice MCQs for CCAT

Correct Answer: B — CPU repeatedly checks device status

Polling: CPU continuously checks if device is ready.

Correct Answer: B — Device signals CPU when ready

Device interrupts CPU when it needs attention.

Correct Answer: A — Direct Memory Access

DMA = Direct Memory Access - transfers data without CPU.

Correct Answer: B — Frees CPU during data transfer

DMA frees CPU to do other work during large data transfers.

Correct Answer: B — I/O devices share memory address space

Memory-mapped I/O: devices accessed like memory locations.

Correct Answer: B — Uses separate I/O address space

Isolated I/O: separate address space with IN/OUT instructions.

Correct Answer: C — DMA

DMA is fastest for large data transfers without CPU involvement.

Correct Answer: B — Communication pathway

Bus is communication pathway between components.

Correct Answer: B — Unidirectional (CPU to memory)

Address bus is unidirectional - CPU sends addresses.

Correct Answer: B — Bidirectional

Data bus is bidirectional - data flows both ways.

Correct Answer: B — CPU continuously checks I/O device status

In programmed I/O, the CPU continuously polls the I/O device status register to check if the device is ready for data transfer.

Correct Answer: B — CPU time is wasted in polling

Programmed I/O wastes CPU cycles as the processor must continuously check device status instead of doing useful work.

Correct Answer: B — DMA Controller

The DMA Controller (DMAC) manages DMA operations, taking over the bus to transfer data between I/O devices and memory.

Correct Answer: B — DMA takes bus control from CPU for one bus cycle at a time

In cycle stealing, DMA controller takes control of the bus for one cycle at a time, interleaving with CPU bus operations.

Correct Answer: B — DMA transfers entire block of data before releasing bus

In burst mode, DMA controller takes control of bus and transfers entire data block before releasing the bus to CPU.

Correct Answer: B — Address used to communicate with I/O device

An I/O port is an address or set of addresses used by the CPU to communicate with a specific I/O device.

Correct Answer: B — Code that executes when an interrupt occurs

ISR is the code that is executed by CPU in response to an interrupt, handling the event that caused the interrupt.

Correct Answer: B — Time from interrupt request to start of ISR execution

Interrupt latency is the delay between when an interrupt is generated and when the ISR begins executing.

Correct Answer: B — Contains addresses of interrupt service routines

The Interrupt Vector Table stores the starting addresses (vectors) of ISRs for each interrupt type.

Correct Answer: B — Interrupt that can be disabled by software

A maskable interrupt can be disabled (masked) by software using the interrupt flag, preventing CPU from responding to it.

Correct Answer: B — Interrupt that cannot be disabled and must be serviced

NMI is a high-priority interrupt that cannot be disabled by software, used for critical events like power failure.

Correct Answer: C — Carrying control signals like read/write

The control bus carries control signals like read/write, clock, interrupt requests, and bus request signals.

Correct Answer: B — Control signal exchange between CPU and device for synchronization

Handshaking is the exchange of control signals between CPU and I/O device to coordinate data transfer timing.

Correct Answer: B — Process of deciding which device gets bus control when multiple devices request it

Bus arbitration determines which of multiple devices requesting bus access should be granted control of the bus.

Correct Answer: B — DMA that operates only when CPU is not using the bus

Transparent DMA transfers data only during cycles when CPU is not using the bus, appearing invisible to CPU operation.