CPU Architecture — Practice MCQs for CCAT

Correct Answer: B — Program Counter

Program Counter (PC) holds address of next instruction to fetch.

Correct Answer: B — Current instruction being executed

IR holds the current instruction being decoded and executed.

Correct Answer: C — Arithmetic and logical operations

ALU (Arithmetic Logic Unit) performs both arithmetic and logical operations.

Correct Answer: B — Control signals

Control Unit generates control signals to coordinate CPU operations.

Correct Answer: B — Top of stack

Stack Pointer holds address of top of stack.

Correct Answer: A — Reduced Instruction Set Computer

RISC = Reduced Instruction Set Computer with simple, fast instructions.

Correct Answer: B — Complex instructions, variable length

CISC (Complex Instruction Set Computer) has complex, variable-length instructions.

Correct Answer: B — Throughput

Pipelining increases throughput by overlapping instruction execution.

Correct Answer: C — 4 or 5

Basic cycle: Fetch, Decode, Execute, Memory, Write-back (4-5 stages).

Correct Answer: C — Control hazard

Control hazard occurs due to branch instructions changing flow.

Correct Answer: B — Holds the address of the next instruction to be fetched

The Program Counter holds the memory address of the next instruction to be fetched from memory.

Correct Answer: C — Instruction Register

The Instruction Register (IR) holds the instruction that is currently being decoded and executed by the CPU.

Correct Answer: B — Holds the address of memory location to be accessed

MAR holds the address of the memory location that is to be read from or written to.

Correct Answer: C — ALU

The Arithmetic Logic Unit (ALU) performs all arithmetic operations (add, subtract) and logical operations (AND, OR, NOT).

Correct Answer: C — Fetch, Decode, Execute

The instruction cycle consists of Fetch (get instruction from memory), Decode (interpret the instruction), and Execute (perform the operation).

Correct Answer: C — Generates control signals to coordinate CPU operations

The Control Unit generates timing and control signals that coordinate the operations of all CPU components.

Correct Answer: B — Memory Buffer Register (MBR)

The Memory Buffer Register (MBR) or Memory Data Register (MDR) temporarily holds data being transferred to or from memory.

Correct Answer: B — Executing multiple instructions simultaneously in different stages

Pipelining allows multiple instructions to be in different stages of execution simultaneously, improving CPU throughput.

Correct Answer: A — Points to the top of the stack in memory

The Stack Pointer contains the address of the top of the stack, used for PUSH and POP operations.

Correct Answer: C — Index Register

Index registers are used for modifying operand addresses during program execution, useful for array indexing and loop counting.

Correct Answer: B — Zero Flag

The Zero Flag (ZF) is set to 1 when the result of an arithmetic or logical operation is zero.

Correct Answer: B — Holds intermediate results of ALU operations

The Accumulator is a special register that holds one operand and the result of ALU operations.

Correct Answer: B — CPU that can execute multiple instructions per clock cycle using multiple execution units

Superscalar architecture has multiple execution units allowing it to execute more than one instruction per clock cycle.

Correct Answer: B — Contains flags indicating the result status of operations

The Condition Code Register or Status Register contains flags (Zero, Carry, Overflow, Sign) that indicate the status of the last operation.

Correct Answer: B — Instruction depends on result of previous instruction not yet available

Data hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed.