CPU Architecture - Practice MCQs for CCAT

Correct Answer: B - Program Counter

Program Counter (PC) holds address of next instruction to fetch.

Correct Answer: C - Current instruction being executed

IR holds the current instruction being decoded and executed.

Correct Answer: A - Arithmetic and logical operations

ALU (Arithmetic Logic Unit) performs both arithmetic and logical operations.

Correct Answer: B - Control signals

Control Unit generates control signals to coordinate CPU operations.

Correct Answer: C - Top of stack

Stack Pointer holds address of top of stack.

Correct Answer: D - Reduced Instruction Set Computer

RISC = Reduced Instruction Set Computer with simple, fast instructions.

Correct Answer: A - Complex instructions, variable length

CISC (Complex Instruction Set Computer) has complex, variable-length instructions.

Correct Answer: B - Throughput

Pipelining increases throughput by overlapping instruction execution.

Correct Answer: C - 4 or 5

Basic cycle: Fetch, Decode, Execute, Memory, Write-back (4-5 stages).

Correct Answer: C - Control hazard

Control hazard occurs due to branch instructions changing flow.

Correct Answer: B - Holds the address of the next instruction to be fetched

The Program Counter holds the memory address of the next instruction to be fetched from memory.

Correct Answer: B - Instruction Register

The Instruction Register (IR) holds the instruction that is currently being decoded and executed by the CPU.

Correct Answer: B - Holds the address of memory location to be accessed

MAR holds the address of the memory location that is to be read from or written to.

Correct Answer: A - ALU

The Arithmetic Logic Unit (ALU) performs all arithmetic operations (add, subtract) and logical operations (AND, OR, NOT).

Correct Answer: A - Fetch, Decode, Execute

The instruction cycle consists of Fetch (get instruction from memory), Decode (interpret the instruction), and Execute (perform the operation).

Correct Answer: B - Generates control signals to coordinate CPU operations

The Control Unit generates timing and control signals that coordinate the operations of all CPU components.

Correct Answer: D - Memory Buffer Register (MBR)

The Memory Buffer Register (MBR) or Memory Data Register (MDR) temporarily holds data being transferred to or from memory.

Correct Answer: B - Executing multiple instructions simultaneously in different stages

Pipelining allows multiple instructions to be in different stages of execution simultaneously, improving CPU throughput.

Correct Answer: D - Points to the top of the stack in memory

The Stack Pointer contains the address of the top of the stack, used for PUSH and POP operations.

Correct Answer: D - Index Register

Index registers are used for modifying operand addresses during program execution, useful for array indexing and loop counting.

Correct Answer: D - Zero Flag

The Zero Flag (ZF) is set to 1 when the result of an arithmetic or logical operation is zero.

Correct Answer: C - Holds intermediate results of ALU operations

The Accumulator is a special register that holds one operand and the result of ALU operations.

Correct Answer: C - CPU that can execute multiple instructions per clock cycle using multiple execution units

Superscalar architecture has multiple execution units allowing it to execute more than one instruction per clock cycle.

Correct Answer: D - Contains flags indicating the result status of operations

The Condition Code Register or Status Register contains flags (Zero, Carry, Overflow, Sign) that indicate the status of the last operation.

Correct Answer: A - Instruction depends on result of previous instruction not yet available

Data hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed.

Correct Answer: A - Arithmetic Logic Unit

The ALU (Arithmetic Logic Unit) performs all arithmetic operations (addition, subtraction, etc.) and logical operations (AND, OR, NOT, etc.) within the CPU.

Correct Answer: C - Decode and execute instructions

The Control Unit fetches instructions from memory, decodes them, and generates control signals to coordinate the execution of instructions by other CPU components.

Correct Answer: D - Program Counter

The Program Counter (PC) holds the memory address of the next instruction to be fetched and executed. It is automatically incremented after each instruction fetch.

Correct Answer: D - Instruction Decode

The standard 5-stage pipeline is: Instruction Fetch (IF) → Instruction Decode (ID) → Execute (EX) → Memory Access (MEM) → Write Back (WB).

Correct Answer: B - A condition that prevents the next instruction from executing in the next clock cycle

A pipeline hazard is a situation that prevents the next instruction in the pipeline from executing during its designated clock cycle, causing stalls or bubbles in the pipeline.

Correct Answer: A - Data hazard

A data hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed execution, creating a read-after-write (RAW) dependency.

Correct Answer: B - Simple, fixed-length instructions

RISC (Reduced Instruction Set Computer) uses simple, fixed-length instructions that can be executed in one clock cycle, with a hardwired control unit and emphasis on register-to-register operations.

Correct Answer: B - Variable-length instructions with complex addressing modes

CISC (Complex Instruction Set Computer) features variable-length instructions, complex addressing modes, and instructions that may take multiple clock cycles to execute.

Correct Answer: C - Data forwarding (bypassing)

Data forwarding (also called bypassing) passes the result of an instruction directly from the pipeline stage where it is produced to the stage where it is needed, without waiting for write-back.

Correct Answer: D - The currently executing instruction

The Instruction Register (IR) holds the instruction that is currently being decoded and executed by the CPU.

Correct Answer: A - k times

In an ideal pipeline with k stages, the speedup is k times compared to a non-pipelined processor, as k instructions can be in different stages of execution simultaneously.

Correct Answer: C - Program Counter

The Program Counter is a special-purpose register that holds the address of the next instruction. Accumulator, Base Register, and Index Register are general-purpose registers used for data manipulation.

Correct Answer: C - A CPU that can execute multiple instructions per clock cycle using multiple pipelines

A superscalar processor has multiple execution units (pipelines) that allow it to dispatch and execute more than one instruction per clock cycle, increasing throughput.

Correct Answer: A - Control hazard

Control hazards occur due to branch instructions. Branch prediction attempts to guess the outcome of a branch before it is resolved, allowing the pipeline to continue fetching instructions speculatively.

Correct Answer: D - Address of the memory location to be accessed

The Memory Address Register (MAR) holds the address of the memory location that is to be read from or written to during a memory access operation.

Correct Answer: D - RISC

RISC processors typically use a hardwired control unit which is faster but less flexible, while CISC processors traditionally use microprogrammed control units to handle complex instructions.

Correct Answer: A - Holds the data being transferred to or from memory

The Memory Data Register (MDR), also called Memory Buffer Register (MBR), holds the data that is being read from or written to the memory location specified by MAR.

Correct Answer: D - The opcode is interpreted and operands are identified

During the decode phase, the control unit interprets the opcode of the instruction, identifies the operands, and generates the appropriate control signals for execution.

Correct Answer: A - To clear all instructions from the pipeline when a branch is mispredicted

A pipeline flush discards all instructions currently in the pipeline. This is necessary when a branch is mispredicted, as the speculatively fetched instructions are invalid and must be discarded.

Correct Answer: B - ARM

ARM (Advanced RISC Machine) processors are the dominant RISC architecture in smartphones and mobile devices due to their low power consumption and high performance-per-watt ratio.

Correct Answer: C - Two instructions try to use the same hardware resource simultaneously

A structural hazard occurs when two or more instructions in the pipeline need to use the same hardware resource (such as memory or an ALU) at the same time.

Correct Answer: A - Stores intermediate results of ALU operations

The accumulator is a register that stores the intermediate results of arithmetic and logical operations performed by the ALU. It serves as an implicit operand in many instructions.

Correct Answer: A - Compiler to detect and schedule parallel operations

VLIW architecture relies on the compiler to detect instruction-level parallelism and pack multiple independent operations into a single long instruction word at compile time.

Correct Answer: C - Zero flag

The Zero flag (Z) is set to 1 when the result of an arithmetic or logical operation is zero, and cleared to 0 otherwise. It is commonly used in conditional branch instructions.

Correct Answer: B - Increases instruction throughput

Pipelining increases instruction throughput by allowing multiple instructions to be in different stages of execution simultaneously, even though the execution time of a single instruction is not reduced.